This invention relates generally to CMOS devices, and more specifically to CMOS structures combining polycrystalline silicon and monocrystalline silicon device.
As MOS circuits become more complex and include more and more devices, it becomes necessary to develop new structures and circuit techniques which minimize the overall size of the fabricated circuit. One such technique for reducing the physical size of a manufactured circuit is to fabricate some of the devices, and generally the load devices, in a overlying layer of semiconductor material. Devices have been fabricated, for example, in which load resistors or MOS load devices have been fabricated in a second, overlying polycrystalline silicon layer.
The manufacture of complex integrated circuits also requires a process which is both high yielding and highly reliable. Such a process is best achieved by minimizing the number of processing steps and by using process steps which are known and well established. Although the need for three dimensional structures in which devices are made in an overlying semiconductor layer are desirable, the proposed structures have not been entirely satisfactory in terms of manufacturability. Additionally, the available structures have not been satisfactory in terms of device characteristics achieved.
Accordingly, a need existed for an improved structure which was both manufacturable and which provided the compactness necessary for complex integrated circuits.
It is therefore an object of this invention to provide an improved CMOS structure having an MOS transistor formed in an overlying layer of semiconductor material.
It is a further object of this invention to provide an improved and compact CMOS inverter structure.
It is another object of this invention to provide an improved CMOS SRAM cell.
It is yet another object of this invention to provide an improved process for fabricating a multiple layer CMOS structure.